Overridden Member System Verilog Classes

Check out below code.

class my_a;
int member1 = 1;
endclass
class my_ea extends my_a;
int member1 = 2;
endclass
Now when I do
my_a A;
my_ea EA;
EA =new();
A=EA;
================================================== ==========
EA = new(); has given handle to object of type my_ea to class variable EA.
A=EA; This pass the same handle (pointer value which points to object of my_ea) to A. so , A.member1 should refer to value 2. But it refer to value 1. 

The reason being is though I have assigned handle of EA to variable A, it will refer its member based on its type.
So A.member1 will refer to member1 based on its type (which is my_a).

Only way base class variable can refer to derived class property is to by declaring them as virtual. In that sense we can refer methods of derived class. system verilog do not support reference to variable.

Now consider below example.

class my_a;
int member1 = 1;
endclass
module test();

my_a a1,a2;

intial

begin

a1 = new();

a1.member1 = 2;

a2=a1;

end

endmodule

Now a2.member1 will refer to value 2. Here both variables' type is same (my_a). So a1 and a2 contains same handle (pointer to which object of type my_a is created). Therefor a1.member1 and a2.member1 will contain same value.