Friday, February 5, 2016

Does System Verilog support Method Overriding and Method Overloading.

Method Overriding : Method of base class enhanced in derived class. Used that as virtual method. Concept of polymorphism

Method Overloading : Multiple method with same name but different signature. Different set of argument .

virtual void print(int x); 
virtual void print(bit y)

This is not supported in System Verilog.

1 comment:

  1. Really awesome... Thanks for sharing this useful content. It's really helped, verification Engineers. If you want to know more information related to inheritance in system Verilog.

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