What is difference between reg ,wire and logic

Difference in very simple terms.

Reg = used to store value. Used in sequential assignments. It will store the value in variable until next assignments.

Wire = used for continuous assignment. Its net (network) type. used for combinational logic. Used in assign statment. It can not store the value. It will connect two port.

Logic :  Logic and reg is slightly different. Logic can also be used for continuous assignment. That mean it can be used at LHS for assign statement.
Implicitly it can be seen as


logic A; //is a shortcut for

var logic A; // This is like Reg A

And

wire A; // is a shortcut for

wire logic A; // This is like wire A


http://inst.eecs.berkeley.edu/~cs150/Documents/Nets.pdf

Wire Elements (Combinational logic) wire elements are simple wires (or busses of arbitrary width) in Verilog designs. The following are syntax rules when using wires:
1. Wire elements are used to connect input and output ports of a module instantiation together with some other element in your design.
2. Wire elements are used as inputs and outputs within an actual module declaration.
3. Wire elements must be driven by something, and cannot store a value without being driven.
4. Wire elements cannot be used as the left-hand side of an = or <= sign in an always@ block.
5. They are the only legal type on the left-hand side of an assign statement.
6. This elements are a stateless way of connecting two pieces in a Verilog-based design.
7. It can only be used to model combinational logic.

Program 1  Legal uses of the wire element

wire A , B , C , D , E ; // simple 1 -bit wide wires
wire [8:0] Wide ; // a 9 -bit wide wire
reg I ;

assign A = B & C ; // using a wire with an assign statement

always @ ( B or C ) begin
I = B | C ; // using wires on the right - hand side of an always@
// assignment
 end

 mymodule mymodule_instance (. In ( D ) ,
 . Out ( E ) ) ; // using a wire as the output of a module

Reg Elements (Combinational and Sequential logic) reg are similar to wires, but can be used to store information (‘state’) like registers. The following are syntax rules when using reg elements.
1. reg elements can be connected to the input port of a module instantiation.
2. reg elements cannot be connected to the output port of a module instantiation.
3. reg elements can be used as outputs within an actual module declaration.
4. reg elements cannot be used as inputs within an actual module declaration.
5. reg is the only legal type on the left-hand side of an always@ block = or <= sign.
6. reg is the only legal type on the left-hand side of an initial block = sign (used in Test Benches).
7. reg cannot be used on the left-hand side of an assign statement.
8. reg can be used to create registers when used in conjunction with always@(posedge Clock) blocks. 9. reg can, therefore, be used to create both combinational and sequential logic.

Program 2 Legal uses of the reg element

wire A , B ;
2 reg I , J , K ; // simple 1 -bit wide reg elements
3 reg [8:0] Wide ; // a 9 -bit wide reg element
4
5 always @ ( A or B ) begin
6 I = A | B ; // using a reg as the left - hand side of an always@
7 // assignment
8 end
9
10 initial begin // using a reg in an initial block
11 J = 1 ’ b1 ;
12 #1
13 J = 1 ’ b0 ;
14 end
15
16 always @ ( posedge Clock ) begin
17 K <= I ; // using a reg to create a positive -edge - triggered register
18 end

When wire and reg Elements are Interchangeable? 

Wire and reg elements can be used interchangeably in certain situations:
1. Both can appear on the right-hand side of assign statements and always@ block = or <= signs.
2. Both can be connected to the input ports of module instantiations.