Setup and Hold time and clocking block in system verilog

Set up time : A time before clock edge for which input data should be stable.

Hold time : A time after clock edge for which input data should be stable.

If any of above is violated the output may go meta-stable.


In above image shaded region before dashed line is setup time. Shaded region after dashed line is hold time. Here it violates setup and hold time.



Above is timing for D flipflop. See here we do not change input in shaded (restricted) region. Input is changed before setup time and remain stable while in hold time.

In system verilog we use clocking block to avoid race condition as well setup/hold violation.

Here I am just giving an idea that how we can use clocking block

module test();
clocking cb @(posedge CLK);
  default input #setup_time output #hold_time;
  output a;
  output b;
  output c;
 
  input x;
  input y;
  input z;
endclocking

We can put clocking block inside module or program.
Here input will be sampled before #setup_time @posedge of CLK.
Output will be driven after #hold_time @posedge of CLK